Memory access is a primary limiting factor in computer performance. While processors have become faster, memory access times have not improved at the same pace. The growing number of computer elements, e.g. multicore processors and hardware accelerators, used to improve computer performance, are competing for access to the same memory, exacerbating this issue. To alleviate this widening memory access gap, memory architectures are evolving and becoming increasingly complex, e.g. multi level caches, local and global memories, and Network on Chip, Uniform Memory Architectures (UMA) or Non-Uniform Memory Architectures (NUMA).
Memory architectures are becoming more complex and different multicore platforms generally have different memory layouts. Multicore applications evolve from one version to the next, are complex and costly and must be portable to a multitude of platforms, with a minimum amount of modification. Managing the memory layout from the application leads to non-portable applications and suboptimal memory utilization. New methods providing a high degree of application portability and optimization are required to take advantage of memory architecture advancement.
Current methods for specifying memory are primarily based on memory segmentation controlled through linker commands, platform specific development and configuration tools and often referencing the memory layout directly “hard-coded” from within the application and other software. These methods are often compiler tool chain dependent, don't provide application portability and platform specific optimization is time consuming and costly.
Accordingly, current solutions are either architecture specific, therefore doesn't provide application portability, or don't provide a sufficient method for handling multicore computer memory, or both, leading to complexity and non-portability. There is a great need for new methods to handle complex multicore computer memory, in a portable manner.